MP2007 1.3-6V 3A, 1.3V–6.0V DDR Memory Termination Regulator MSOP8

Product

MP2007 1.3-6V 3A, 1.3V–6.0V DDR Memory Termination Regulator MSOP8

Share

pMPS MP2007 — 3A, 1.3V–6.0V DDR Memory Termination Regulator, 1.3-6V input, 3 A output, MSOP8./p

[email protected]

MPS MSOP8 Power Management LDO Regulators

Product Details
Download

MP2007 1.3-6V 3A, 1.3V–6.0V DDR Memory Termination Regulator MSOP8

The MPS MP2007 is a 3A, 1.3V–6.0V DDR Memory Termination Regulator. It operates from a 1.3 V to 6 V input and is rated for 3 A. It is supplied in a MSOP8 package.

The MP2007 integrates the DDR memory termination regulator with the output voltage (VTT) and a buffered VTTREF outputs is a half of VREF.

Key Specifications

Part Number	MP2007
Function	3A, 1.3V–6.0V DDR Memory Termination Regulator
Input Voltage	1.3 V to 6 V
Current Rating	3 A
Package	MSOP8
Lifecycle	NRFND
Ordering Codes	MP2007

Features

VDDQ Voltage Range: 1.3V to 6.0 V
Up to 3A Integrated Sink/Source Linear Regulator with Accurate VREF/2 Divider Reference for DDR Termination
Requires Only 20uF Ceramic Output Capacitance
Drive Voltage Range: 4.5 V to 5.5 V
1.3V Input (VDDQ) Helps Reduce Total Power Dissipation
Integrated Divider Tracks VREF for VTT and VTTREF
Kelvin Sensing (VTTSEN)
±20mV Accuracy for VTT and VTTREF
Built-In Soft-Start, UVLO and OCL
Thermal Shutdown

Typical Application Circuit

Applications

Notebook DDR2/3 Memory Supply and Termination Voltage in ACPI Compliant

Design Notes

Dissipation is (VIN − VOUT) × IOUT. Check it against the package thermal resistance at the real ambient temperature before committing to the full rated current.
Some low-noise LDOs require a minimum output capacitor ESR for loop stability — read the stability section before substituting a ceramic part.
Add a bypass capacitor on the reference pin where provided; it sets the output noise floor.
PSRR falls as the input-to-output differential shrinks, so headroom matters at low VIN.